In general, for exchanging data between two digital circuits operating at different clock rates, a rate converter is needed for converting the data rate.
For example, when exchanging digital video signals between a digital video signal processing circuit of an imager operating at a clock rate of 18 MHz and a digital video signal processing circuit of a digital video tape recorder (RVTR) operating at a clock rate of 13.5 MHz pursuant to D1 standard, a rate converter, such as a 4:3-down rate converter for converting the rate of digital video signal outputted from the imager from 18 MHz to 13.5 MHz, or a 3:4-up rate converter for converting the rate of digital video signals outputted from the DVTR from 13.5 MHz to 18 MHz, is needed.
The-imager employing a solid-state imaging device usually has a clock rate determined by the number of pixels of the solid-state imaging device. For example, with an imager employing 500,000 pixel solid imaging devices, the digital video signal processing circuit operates at a clock rate of 18 MHz.
With the conventional rate converter, output data of a desired output clock rate is obtained by upconverting input data to a clock rate equal to the least common multiple of the input clock rate and the output clock rate and by thinning out via a, filter. Thus the conventional rate converter is in need of filtering at the output clock rate equal to the above-mentioned least common multiple.
For example, with a 4:3-down rate converter, input data at the 18 MHz clock rate is converted by the filtering shown in FIGS. 1 and 2 into output data having the clock rate of 13.5 MHz.
That is, with the 4:3-down rate converter, zero data is inserted at the positions of 18 MHz clock rate input data {X.sub.m } shown at A in FIG. 1 which can become sampling points for 13.5 MHz as shown at B in FIG. 1 for upconverting the input data to the clock rate of a frequency equal to the least common multiple of 18 MHz and 13.5 MHz, that is 54 MHz. Thus, in the frequency domain, the frequency components repeated on the basis of 18 MHz as shown at A in FIG. 2 are now repeated at the unit of repetition of 54 MHz, with the frequency characteristics remaining unchanged, as shown at B in FIG. 2.
The 54 MHz clock rate data is then passed through a filter having characteristics shown at C in FIG. 1 and at C in FIG. 2. That is, since the output clock rate is 13.5 MHz, should there be frequency components of not less than 6.75 MHz (one-half of 13.5 MHz) up to 27 MHz (one-half of 54 MHz), aliasing is produced when the clock rate is set to 13.5 MHz, and hence original frequency characteristics cannot be maintained. Consequently, the data is passed through a low-pass filter for suppressing frequency components not less than 6.75 MHz.
The data {Y.sub.i } at the clock rate of 54 MHz, having frequency components not less than 6.75 MHz suppressed, is obtained as data Y.sub.1 to Y.sub.14, that is, ##EQU1## by filtering input data X.sub.m .times.z.sup.m .multidot.X.sub.1 with a transfer function represented by the formula (1) ##EQU2## using a transversal filter operating at 54 MHz, with the number of taps being 12.
From the data {Y.sub.i }, with the clock rate of 54 MHz, as shown at D in FIGS. 1 and 2, every three data of i=3n, i=3n+1 or i =3n+2 is extracted at the clock rate of 13.5 MHz as shown at E in FIG. 1, whereby output data {Y.sub.n } with the clock rate of 13.5 MHz, in which frequency characteristics of the input data {X.sub.m } are maintained to the maximum extent, is obtained, as shown at E in FIG. 2.
With the 3:4-up rate converter, the input data {X.sub.n } with the clock rate of 13.5 MHz is converted into output data {Y.sub.m } with the clock rate of 18 MHz by the filtering shown in FIGS. 3 and 4.
That is, with the 3:4-up rate converter, zero data is inserted at the positions of 13.5 MHz clock rate input data {X.sub.m } shown at A in FIG. 3 which can become sampling points for 18 MHz as shown at B in FIG. 3, for upconverting the input data to the clock rate of a frequency equal to the least common multiple of 18 MHz and 13.5 MHz, that is 54 MHz. Thus, in the frequency domain, the frequency components repeated on the basis of 13.5 MHz as shown at A in FIG. 4 are now repeated at the unit of repetition of 54 MHz, with the frequency characteristics remaining unchanged, as shown at B in FIG. 4.
The data having the clock rate of 54 MHz is then passed through a filter having characteristics shown at C in FIGS. 3, 4. That is, since the output clock rate is 18 MHz, should there be frequency components of not less than 9 MHz (one-half of 18 MHz) up to 27 MHz (one-half of 54 MHz), aliasing is produced when the clock rate is set to 18 MHz, and hence original frequency characteristics cannot be maintained. Consequently, the data is passed through a low-pass filter for suppressing frequency components not less than 9 MHz.
The data {Y.sub.i } at the clock rate of 54 MHz, having frequency components not less than 9 MHz suppressed, is obtained as data Y.sub.1 to Y.sub.14, that is, ##EQU3## by filtering input data X.sub.m =z.sup.m .multidot.X.sub.1 with a transfer function represented by the formula (2) ##EQU4## using a transversal filter operating at 54 MHz, with the number of taps being 12.
From the data {Y.sub.i }, with the clock rate of 54 MHz, as shown at D in FIGS. 3 and 4, every four data of i=4m-2, i=4m-1 i=4m or i=4m-3 is taken out at the clock rate of 18 MHz as shown at E in FIG. 3, so that output data {X.sub.n } with the clock rate of 18 MHz, in which frequency characteristics of the input data {X.sub.m } are maintained to the maximum extent, is obtained, as shown at E in FIG. 4.
With a M:N (M&gt;N), such as 5:3, down rate converter, in which rate conversion of 5:3 is executed for converting f.sub.SH rate input data {X.sub.m } into f.sub.SL rate output data {Y.sub.n }, every two "O"s are inserted between respective data of the f.sub.SH rate input data {X.sub.m } in order to generate 3 f.sub.SH rate data {Y.sub.i } which is filtered by a transversal filter operating at the 3 f.sub.SH rate. Every five data is sampled from the 3 f.sub.SH rate data {Y.sub.i } to generate data {Y.sub.n } having the rate of f.sub.SL (F.sub.SL =3/5 f.sub.SH).
That is, by inserting two "0"s as shown at B in FIG. 5 between data of the f.sub.SH rate input data as shown at A in FIG. 5 for up-conversion to the 3 f.sub.SH rate and by subsequently passing the up-converted data by a transversal filter operating at the 3 f.sub.SH rate by convolution by the coefficients shown at C in FIG. 5, data Y.sub.1 to Y.sub.16 ##EQU5## are generated.
From the data {Y.sub.i }, with the rate of 3 f.sub.SH, as shown at D in FIG. 5, every five data of i=5n-4, i=5n-3 i=5n-2, i=5n-1 or i=5n, output data {Y.sub.n } having the rate of f.sub.SL, is obtained, as shown at E in FIG. 5.
With a M:N (M&lt;N), such as 3:5, up rate converter, in which rate conversion of 3:5 is executed for converting f.sub.SL rate input data {X.sub.m } into f.sub.SH rate output data {Y.sub.n }, every four "0"s are inserted between the f.sub.SL rate input data {X.sub.m } in order to generate 5 f.sub.SL rate data {Y.sub.5n } which is filtered by a transversal filter operating at the 5 f.sub.SL rate. Every three data is sampled from the 5 f.sub.SL rate data {Y.sub.5n } to generate data {Y.sub.m } having the rate of f.sub.SH (F.sub.SH =5/3 f.sub.SL).
That is, by inserting four "0"s as shown at B in FIG. 6 between data of the f.sub.SL rate input data as shown at A in FIG. 6 for up-conversion to the 5 f.sub.SL rate and by subsequently passing the up-converted data by a transversal filter operating at the 5 f.sub.SL rate by convolution by the coefficients shown at C in FIG. 6, data Y.sub.1 to Y.sub.19 ##EQU6## are generated.
From the data {Y.sub.i }, with the rate of 5 f.sub.S1, as shown at D in FIG. 6, every three data of i=3n-2, i=3n-13 or i=3n is extracted, whereby output data {Y.sub.m } having the rate of f.sub.SH, is obtained, as shown at E in FIG. 6.
With the camera built-in type DVTR having an imager operating at a clock rate of 18 MHz and a DVTR pursuant to the D1 standard operating at the clock rate of 13.5 MHz, integrated thereto, or a so-called digital camcorder, it is necessary to have both the above-mentioned down rate converter and the up rate converter, resulting in a large-sized circuit arrangement because of these rate converters.
On the other hand, with the conventional rate converter, it is necessary to have a fast arithmetic-logical unit for executing filtering at a clock rate equal to the least common multiple of the input and output clock rates.
With the 4:3 down rate converter for converting the 18 MHz clock rate input data {Y.sub.m } into 13.5 MHz clock rate output data {Y.sub.n }, the data {Y.sub.i } having the clock rate of 54 MHz, which is the least common multiple of the 13.5 MHz input clock rate and the 18 MHz output clock rate, obtained by the filtering by the transfer function F.sub.1 (z) shown by the formula (1), can be classed into the following three groups, depending on coefficients:
The first group is made up of i=3n-1 data {Y.sub.(3n-1) } having coefficients {k.sub.0, k.sub.3, k.sub.6, k.sub.9 }, such that ##EQU7##
The second group is made up of i=3n data {Y.sub.(3n) } having coefficients {k.sub.1, k.sub.4, k.sub.7, k.sub.10 }, such that ##EQU8##
The third group is made up of i=3n-2 data {Y.sub.(3n-2) } having coefficients {k.sub.2, k.sub.5, k.sub.8, k.sub.11 }, such that ##EQU9##
The data {Y.sub.(3n-1) } having the group of coefficients {k.sub.0, k.sub.3, k.sub.6, k.sub.9 } may be obtained using a transversal filter of the transfer function Fa(z), that is EQU Fa(z)=k.sub.0 +k.sub.3 .multidot.z.sup.-1 +k.sub.6 .multidot.z.sup.-2 +k.sub.9 .multidot.z.sup.-3
The data {Y.sub.(3n) } having the group of coefficients {k.sub.1, k.sub.4, k.sub.7, k.sub.10 } may be obtained using a transversal filter of the transfer function Fb(z), that is EQU Fb(z)=k.sub.1 +k.sub.4 .multidot.z.sup.-1 +k.sub.7 .multidot.z.sup.-2 +k.sub.10 .multidot.z.sup.-3
In addition, the data {Y.sub.(3n-2) } having the group of coefficients {k.sub.2, k.sub.5, k.sub.8, k.sub.11 } may be obtained using a transversal filter of the transfer function Fc(z), that is EQU Fc(z)=k.sub.2 +k.sub.5 .multidot.z.sup.-1 +k.sub.8 .multidot.z.sup.-2 +k.sub.11 .multidot.z.sup.-3
Consequently, with the 4:3 down rate converter, the output data {Y.sub.n } may be calculated by parallel operation of three transversal filters performing the filtering with the transfer functions Fa(z), Fb(z) and Fc(z) at the input clock rate of 18 Mhz, in place of upconverting the input data of 18 Mhz clock rate {X.sub.m } to the clock rate of 54 MHz (the least common multiple) by inserting zero data.
Similarly, with the up rate converter of converting the input data with the 13.5 MHz clock rate {X.sub.n } into output data {Y.sub.m } with the 18 MHz clock rate, the data {Y.sub.i } with the clock rate of 54 MHz, corresponding to the least common multiple of the 18 MHz output clock rate and the 13.5 MHz clock rate resulting from filtering by the transfer function F.sub.2 (z) shown by the formula (2), may be classed into four groups, namely i=4m-2 data {Y.sub.(4m-2) } having a first group of coefficients {k.sub.0, k.sub.4, k.sub.8 }, i=4m-1 data {Y.sub.(4m-1) } having a second group of coefficients {k.sub.1, k.sub.5, k.sub.9 }, i=4m data {Y.sub.(4m) } having a third group of coefficients {k.sub.2, k.sub.6, k.sub.10 } and i=4m-3 data {Y.sub.(4m-3) } having a fourth group of coefficients {k.sub.3, k.sub.7, k.sub.11 }. Thus the output data {Y.sub.m } may be calculated by parallel operation of four transversal filters performing the filtering with the transfer functions EQU Fa(z)=k.sub.0 +k.sub.4 .multidot.z.sup.-1 +k.sub.8 .multidot.z.sup.-2 EQU Fb(z)=k.sub.1 +k.sub.5 .multidot.z.sup.-1 +k.sub.9 .multidot.z.sup.-2 EQU Fc(z)=k.sub.2 +k.sub.6 .multidot.z.sup.-1 +k.sub.10 .multidot.z.sup.-2 EQU Fd(z)=k.sub.3 +k.sub.7 .multidot.z.sup.-1 +k.sub.11 .multidot.z.sup.-2
at the input clock rate of 13.5 MHz, in place of upconverting the input data of 13.5 MHz clock rate {X.sub.n } to the clock rate of 54 MHz (the least common multiple) by inserting zero data.
By such parallel operation of the plural transversal filters at an input clock rate, the necessity of providing a fast transversal filter operated at the clock rate equal to the least common multiple of the input and output clock rates is eliminated. However, plural transversal filters become necessary.
Up to now, a register pre-fix type transversal filter and a register post-fix type transversal filter have been known.
With the register pre-fix type transversal filter, as shown in FIG. 7, a time difference of a unit time {z.sup.-1 } corresponding to one clock is applied to the input data {X.sub.n } by delay circuits 1A, 2A and 1C. The delayed data is then multiplied by the filter coefficients {k.sub.1, k.sub.2, k.sub.3 and k.sub.4 } by multipliers 2A, 2B, 2C and 2D, and the resulting products are summed by an additive unit 3 to generate output data Y such that EQU Y=k.sub.1 .multidot.X.sub.4 +k.sub.2 (z.sup.-1 .multidot.X.sub.3)+k.sub.3 (z.sup.-2 .multidot.X.sub.2)+k.sub.4 (z.sup.-3 .multidot.X.sub.1)
For a rate converter, a register-prefix type transversal filter has been in use. However, such register-prefix type transversal filter is in need of a multi-input additive unit as the additive unit 3. In addition, a hold time need be provided for the shift register. Thus the register-prefix type filter is unfit for fast operation.
On the other hand, with the register-postfix type transversal filter, as shown in FIG. 8, the input data {X.sub.n } is multiplied with filter coefficients {k.sub.1, k.sub.2, k.sub.3 and k.sub.4 }, by multipliers 4A, 4B, 4C and 4D, and a time difference of a unit time {z.sup.-1 } is applied to the resulting products. The delayed products are then summed by additive units 6A, 6B and 6C to generate output data Y such that EQU Y=k.sub.1 .multidot.X.sub.4 +(k.sub.2 .multidot.X.sub.3)z.sup.-1 +(k.sub.3 .multidot.X.sub.2)z.sup.-2 +(k.sub.4 .multidot.X.sub.1)z.sup.-3
With the register post-fix type transversal filter, the delay circuit constituting a shift register is simultaneously used as a pipeline register. Besides, since the additive units are connected between the delay circuits, there is no necessity of providing the hold time. Thus it is of an efficient circuit configuration for fast operation with the aid of a fast process. However, since zero is inserted in the input data in the up rate conversion, a data hold operation becomes necessary during filtering. However, such data holding operation cannot be performed with the register postfix type transversal filter because there is no register ahead of each multiplier.
It is therefore an object of the present invention to provide the rate converter and the imager constructed in the following manner.
Thus it is an object of the present invention to provide a rate converter in which rate conversion may be achieved by a sole transversal filter without necessitating a fast transversal filter operated at a clock rate equal to the least common multiple of the input and output clock rates.
It is another object of the present invention to provide a bidirectional rate converter having the functions of both the down rate converter and the up rate converter.
It is another object of the present invention to provide a bidirectional rate converter in which the circuit scale is diminished by using a common filtering means for the down rate converter and the up rate converter.
It is also an object of the present invention to provide an imager which may be reduced in size.